fir_top Project Status
Project File:	fir_demo.xise	Parser Errors:	No Errors
Module Name:	fir_top	Implementation State:	New
Target Device:	xc6slx9-3tqg144	Errors:
Product Version:	ISE 13.2	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated
ISIM Simulator Log	Current	ΦάΘΥ ΞεΤΒ 6 20:27:38 2012

Date Generated: 05/06/2012 - 20:29:02